Silicon Modules and MACs Meeting 24 July 2024

https://indico.cern.ch/event/1439523/

 The main focus will be ESD-induced loss of 50% of channels in HGCROCs. A meeting was held on this subject at CERN last week and we agreed to hold a follow-up meeting on July 24th. Paul Aspell prepared a [summary](https://indico.cern.ch/event/1436473/contributions/6044799/attachments/2893045/5071864/ESD.pdf) of the issue that you can look over in preparation for this meeting.

We would like each MAC to prepare a slide or two from their records covering cases of having seen 1/2 chip losses in hexaboards and modules going back as far in time as possible. Please try to include information about what was done with the hexaboard or module before the issue was seen.

For modules being built soon, Rong-Shyang prepared a [document](https://docs.google.com/document/d/17d-srYzMhzHcfaJUh_QdVGQBLdzKwAE3e4Dl8biNCqE/edit?usp=sharing) on ESD protection that MACs can reasonably be able to use. It also discusses some additional testing that is needed, for the time being, to help track exactly at what step in hexaboard/module handling/processing the 1/2 chip losses may occur.